[SGVLUG] Linux Sonoma (Centrino) Support

[Chris Smith]

On 9/20/05, Dustin <laurence at alice.caltech.edu> wrote:
> On Tue, 20 Sep 2005, Chris Smith wrote:
> Hmm, I thought Sony Vaios were fairly well liked among Linux folk?

We're masochists. ;-) I think the poser value of having a flashy
looking laptop won out over the "how much can I do with Linux?"
factor.

I do think some Sony's are pretty good in the compatibility department
these days, but you have to be careful.
 
> > I think the big thing, that Intel failed to be properly prepared for,
> > was the total failure of the Itanium to take market share by now. The
> 
> Whether true or not, and putting on my most prejudiced hat, I always like
> to imagine that the big mistake was in thinking that the purchasers of
> high-end servers somehow care about that amusing company that makes those
> little chips for home computer toys. :-)

Yeah, I don't think that was really that much of a mistake. Note that
most super computer clusters run on Intel chips, and for that matter
Intel has the largest share of the "high-end server" business. Just
not Itanium (and Itanium's numbers are the kind that only Intel could
or should be embarassed about).

Right now, Itanium2's are the go-to chips for raw floating-point
performance (although IBM's POWER5 stuff is right on their tail, but
they don't have nearly as broad a base of vendors), and those who care
about such things are very much aware of it. We just aren't that
excited because when it comes to integer performance, the x86 chips
still beat it.

> Hmm...isn't Transmeta's architecture also VLIW under the hood?  Was there
> some connection to closing the door that Transmeta was trying to slip
> through, or did they just both listen to the same academic fashion for
> VLIW (huh, wonder what the fashionable kool-aid is nowadays--cell maybe)?
> You could run a field of Crusoes on the power requirements of one Itanic,
> though, so maybe not.

The original designs for the Itanium were totally designed for
performance at all costs (particularly for the Itanium1, which was
clearly going to disappoint, so they needed to do as much as possible
to avoid total embarassment), but the key thing is that in principle
the chips avoid having to have an instruction rescheduler and all the
register renaming, completion unit, etc. complexity that really does
jack up your power budget. Similar to the Crusoe as well, it's much
easier to power down a processing unit if it isn't being used. So,
while they new that their initial designed were going to target the
high-end users, in order to establish a beach head, they were
expecting to be able to deploy the architecture throughout their
product line.

> Hmm, interesting question--if you sheared off the translation layer and
> made a chip that really did just execute it's native underlying
> instructions, what would you get?  How many transistors and how many watts
> would you save?  I'm not enough of a hardware guy to know.

Not very much. This is the fundamental game that PowerPC came to
market just a tad too late to really exploit. When the original PPro
came out, I seem to recall something like 15% of the it's transistor
budget (might have been 5%) was for instruction translation. However,
the number of transistors needed for doing translation has remained
essentially fixed, while transistor budgets have followed Moore's Law.
So these days it's a very tiny fraction of the chip, and it is more
than compensated for by the increased volume you can get from
compatibility. This is why VIA makes x86 compatible chips rather than
some other ISA.
 
> Way back when, my uninformed preference was for Motorola, then Alpha, then
> PPC as the only competing ISA left standing.  The latter is still true,
> but we have to wait and find out if game machines are more influential now
> than desktops. :-)

Yeah, and when you look at the PPC ISA, it's only slightly less ugly than x86.

> > I actually have a dual-PPro machine from the "good ol' days". Those
> > things were fantastic for running Linux. ;-)
> 
> I seem to recall something like that.  If all that cache wasn't so
> expensive...all that L2 cache seems to be a strength of the P-M, too, so
> there's more continuity for ya.

>From what I understand, cache is actually fairly cheap compared to
just about anything else you can do with your transistor budget. They
tend to be far more compact and fault-free than other parts of a chip.

> Must be easier to write high-performance code for than the P4, too.

Having a shorter pipeline really, really helps. The P4's deep pipeline
requires almost the same kind of challenging thinking needed for EPIC.

-- 
Chris